An FPGA-based Point Pattern Matching Processor with Application to Fingerprint Matching

We describe the design and synthesis of a high-performance coprocessor for point pattern matching with application to ngerprint matching using Splash 2-an attached processor for SUN SPARCstation hosts. Each of the eld programmable gate array (FPGA)-based processing elements (PEs) is programmed using VHDL behavioral modeling. Using the simulation tools, the program logic is veriied. The nal control bit stream for the PEs is generated using the synthesis tools. The point feature matching coprocessor can run at a peak speed of 17.1 MHz per feature vector of a n-gerprint. With 65 features per ngerprint, the matching speed has been projected at the rate of 2:610 5 n-gerprints/sec. The synthesized coprocessor was tested on a 10,000 ngerprint database.